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  r07ds0925ej0400 rev.4.00 page 1 of 6 mar 22, 2013 preliminary datasheet rjk0393dpa 30v, 40a, 4.3m ? max. n channel power mos fet high speed power switching features ? high speed switching ? capable of 4.5v gate drive ? low drive current ? high density mounting ? low on-resistance ? pb-free ? halogen-free outline renesas package code: pwsn0008de-a (package name: wpak(3f)) g d sss ddd 4 123 5678 1, 2, 3 source 4 gate 5, 6, 7, 8 drain 876 5 2 1 34 absolute maximum ratings (ta = 25c) item symbol ratings unit drain to source voltage v dss 30 v gate to source voltage v gss ? 20 v drain current i d 40 a drain peak current i d(pulse) note1 160 a body-drain diode reverse drain current i dr 40 a avalanche current i ap note 2 16 a avalanche energy e ar note 2 25.6 mj channel dissipation pch note3 40 w channel to case thermal impedance ? ch-c 3.13 ?c/w channel temperature tch 150 ?c storage temperature tstg ?55 to +150 ?c notes: 1. pw ? 10 ? s, duty cycle ? 1% 2. value at tch = 25 ?c, rg ? 50 ? 3. tc = 25 ?c r07ds0925ej0400 rev.4.00 mar 22, 2013
rjk0393dpa preliminary r07ds0925ej0400 rev.4.00 page 2 of 6 mar 22, 2013 electrical characteristics (ta = 25c) item symbol min typ max unit test conditions drain to source breakdown voltage v (br)dss 30 ? ? v i d = 10 ma, v gs = 0 gate to source leak current i gss ? ? ? 0.1 ? a v gs = ? 20 v, v ds = 0 zero gate voltage drain current i dss ? ? 1 ? a v ds = 30 v, v gs = 0 gate to source cutoff voltage v gs(off) 1.2 ? 2.5 v v ds = 10 v, i d = 1 ma r ds(on) ? 3.3 4.3 m ? i d = 20 a, v gs = 10 v note4 static drain to source on state resistance r ds(on) ? 4.2 5.9 m ? i d = 20 a, v gs = 4.5 v note4 forward transfer admittance |y fs | ? 100 ? s i d = 20 a, v ds = 10 v note4 input capacitance ciss ? 3270 ? pf output capacitance coss ? 430 ? pf reverse transfer capacitance crss ? 225 ? pf v ds = 10 v, v gs = 0, f = 1 mhz gate resistance rg ? 1.4 ? ? total gate charge qg ? 21 ? nc gate to source charge qgs ? 9.5 ? nc gate to drain charge qgd ? 4.7 ? nc v dd = 10 v, v gs = 4.5 v, i d = 40 a turn-on delay time t d(on) ? 13.2 ? ns rise time t r ? 6.0 ? ns turn-off delay time t d(off) ? 52 ? ns fall time t f ? 7.1 ? ns v gs = 10 v, i d = 20 a, v dd ? 10 v, r l = 0.5 ? , rg = 4.7 ? body?drain diode forward voltage v df ? 0.83 1.08 v if = 40 a, v gs = 0 note4 body?drain diode reverse recovery time t rr ? 23.5 ? ns if = 40 a, v gs = 0 di f / dt = 100 a/ ? s notes: 4. pulse test
rjk0393dpa preliminary r07ds0925ej0400 rev.4.00 page 3 of 6 mar 22, 2013 main characteristics channel dissipation pch (w) case temperature tc (c) power vs. temperature derating drain to source voltage v ds (v) gate to source voltage v gs (v) drain current i d (a) maximum safe operation area 80 60 40 20 0 50 100 150 200 100 10 1 0.1 0.1 0.3 1 3 10 30 100 1000 tc = 25 c 1 shot pulse operation in this area is limited by r ds(on) 1 ms dc operation 10ms gate to source voltage v gs (v) static drain to source on state resistance r ds(on) (m) drain to source saturation voltage vs. gate to source voltage drain current i d (a) static drain to source on state resistance vs. drain current 200 160 120 80 40 0 4 8 12 16 20 20 10 2 5 1 30 300 pulse test i d = 20 a 5 a 10 a 1 10 100 1000 3 100 50 v gs = 4.5 v 10 v pulse test drain to source voltage v ds (v) drain current i d (a) typical output characteristics drain current i d (a) typical transfer characteristics 50 40 30 20 10 0 246810 50 40 30 20 10 0 1234 5 tc = 75c 25c ?25c v ds = 10 v pulse test v gs = 2.4 v 10 v 4.5 v 2.5 v pulse test 2.7 v 2.9 v 10 s 100 s drain to source saturation voltage v ds(on) (mv)
rjk0393dpa preliminary r07ds0925ej0400 rev.4.00 page 4 of 6 mar 22, 2013 case temperature tc (c) static drain to source on state resistance vs. temperature 10 8 6 4 2 ?25 0 25 50 75 150 100 125 0 v gs = 4.5 v 10 v i d = 5 a, 10 a, 20 a 5 a, 10 a, 20 a capacitance c (pf) drain to source voltage v ds (v) typical capacitance vs. drain to source voltage 0 102030 10000 3000 1000 300 100 30 10 ciss coss crss v gs = 0 f = 1 mhz 50 40 30 20 10 0 20 16 12 8 4 10 20 30 40 50 0 i d = 40 a v gs v ds v dd = 25 v 10 v v dd = 25 v 10 v gate charge qg (nc) drain to source voltage v ds (v) gate to source voltage v gs (v) dynamic input characteristics source to drain voltage v sd (v) reverse drain current i dr (a) 50 40 30 20 10 0 0.4 0.8 1.2 1.6 2.0 reverse drain current vs. source to drain voltage 5 v 10 v 50 40 30 20 10 25 50 75 100 125 150 0 channel temperature tch (c) repetitive avalanche energy e ar (mj) maximum avalanche energy vs. channel temperature derating static drain to source on state resistance r ds(on) (m) pulse test pulse test i ap = 16 a v dd = 15 v duty < 0.1% rg 50 v gs = 0, ?5 v
rjk0393dpa preliminary r07ds0925ej0400 rev.4.00 page 5 of 6 mar 22, 2013 1 pulse width pw (s) normalized transient thermal impedance vs. pulse width 1 m 10 m 100 m 10 100 10 10 1 0.1 0.01 d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot pulse vin monitor d.u.t. vin 10 v r l v ds = 10 v t r t d(on) vin 90% 90% 10% 10% vout t d(off) vout monitor 90% 10% t f switching time test circuit switching time waveform rg d. u. t rg i ap monitor v ds monitor v dd 50 vin 15 v 0 i d v ds i ap v (br)dss l v dd e ar = l ? i ap 2 ? 2 1 v dss v dss ? v dd avalanche test circuit avalanche waveform normalized transient thermal impedance s (t) dm p pw t d = pw t ch ? c(t) = s (t) ? ch ? c ch ? c = 3.13c/w, tc = 25 c
rjk0393dpa preliminary r07ds0925ej0400 rev.4.00 page 6 of 6 mar 22, 2013 package dimensions 4.23typ 5.9 0.21typ 0.85max 6.1 1.27typ +0.1 -0.2 +0.1 -0.3 1.27typ 0.05max 0min 0.545typ stand-off 5.1 0.2 4.90 0.1 0.5 0.15 3.6 0.20 .5 0.15 0.42 0.08 3.92 0.22  pw s n 0008 de- a w pak ( 3f )v 0.075 g mass[t y p. ] rene s a s c od e jeita packa g e cod e previous c od e (sn plating) notice:the reverse pattern of die-pad support lead described above exists. unit: mm packa g e nam e w pak ( 3f ) ordering information orderable part number quan tity shipping container RJK0393DPA-00-J5A 3000 pcs taping note: the symbol of 2nd "-" is occasionally presented as "#".
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. 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